The present disclosure relates to integrated circuit (IC) fabrication, and more specifically, to an interconnect structure and a method for forming the same.
Integrated circuit (IC) chips can include billions of interconnected devices, such as transistors, resistors, capacitors, and diodes, etc., located in layers of materials. The quality and viability of an IC chip is partially dependent on the techniques used for fabricating and packaging the IC chips and the structure of various components therein. Fabrication of an IC chip can include two phases: front-end-of-line processes (FEOL) and back-end-of-line processes (BEOL). FEOL generally includes fabrication processes performed on a wafer up to and including the formation of gate materials (e.g., a polysilicon gate) for a transistor structure. A group of vertically-extending conductive contacts can provide electrical connections to the transistor from other functional elements of a circuit. BEOL generally includes fabrication processes following the formation of materials in FEOL processing, including the formation of interconnect structures for connecting the devices therebelow. An interconnect structure can include a multitude of stacked and electrically connected metal structures positioned in metal levels. For example, an interconnect structure can include metal wires oriented parallel to the semiconductor substrate in metal wire layers. The interconnect structure may further include metal vias oriented perpendicular to the semiconductor substrate in via layers between the metal wire for connecting the metal wires of various layers.
Efficient routing of interconnects, across semiconductor devices, requires formation of multi-level patterning schemes, such as single or dual damascene interconnect structures. For example, in single damascene processes for forming interconnect structures a via layer, also known as an inter-level dielectric (ILD) region, may be formed including metal vias therein, and subsequently a metal wire layer may be separately formed above the via layer including metal wires contacting the metal vias therebelow. In contrast, in dual damascene processes for forming interconnect structures, openings for the vias and wires may be formed in such a way that the conductive metal material fills the via and wire openings during the same deposition process to form the metal wires and metal vias.
One challenge associated with conventional dual- and single- damascene processes for forming interconnect structures is the lack of control over the etch profile between the metal wire and metal via structures. For example, it may be difficult to control the depth of the wire opening with respect to the via opening therebelow. Additionally, during the formation of the wire opening, etching of the exposed upper portions of the via opening may cause chamfering of the via opening sidewalls. Another challenge associated with the conventional dual-damascene formation of interconnect structures may include damage caused to exposed structures underlying the via opening during the removal of the hard mask used to form the via and wire openings.